In order to synchronize the receiver apparatus, digital receive-transmit systems are usually required to send information based on the clock frequency of a data source, which may be represented eg. by the source of a digital video signal. It is known, for instance, to measure the clock frequency of the data source compared to the transmission frequency of the transmitter system data, which is already known as such to the receiver apparatus. The value of the frequency measurement, duly coded, will then be sent to the receiver apparatus where it is decoded and used for clocking purposes.
FIG. 1 shows an example of a frequency measuring system of the data source as described in ETSI ITU-J81 Standard, to transmit a digital television signal on a 34368 Kb/s flow.
An ET system is described showing a transmission flow FT sent at a frequency FQ2 of 34368 KHz to a suitable frequency divider DT, which divides frequency FQ2 of the transmission flow FT by 4296 and supplies a sampling signal SC at a measuring frequency FP of 8 KHz. Said sampling signal SC is sent in fact to a pilot input IP of a sampler CP. A data flow FS from a video source not shown here, feeds a counter modulo-2 C1 at a rated frequency FQ1 of 27 MHz, which outputs a signal SD at a halved frequency FD, i.e. 13,5 MHz. Said signal SD enters the signal input IS of the sampler CP where it is sampled. Since the number of cycles counted within a time interval of 125 .mu.s corresponding to the measuring frequency FP of 8 KHz of the sampling signal SC is theoretically 1687.5, a coded U signal having alternatively 0 and 1 values in an interval of 125 .mu.s is obtained from the sampler output CP provided the data flow SF always maintains its rated frequency FQ1, where 0 corresponds to 1687 cycles counting and 1 to 1688 cycles counting. Therefore, ET system measures the frequency FQ1 of the data flow FS based on one-cycle precision and supplies it based on one-cycle precision to a receiver R. Said receiver R is known as such and will not be further described in detail, as its implementation opportunities are quite varied. Said receiver R contains anyway a phase locked loop PLL, that could for instance be designed according to the known state of art to substantially input receive the coded signal U, which is a digital signal, make a phase comparison with a previously stored phase value and supply analogically the comparison result through a lowpass filter to a controlled oscillator under voltage supplying the frequency FQ1 to the receiver R.
It should be noted for a better understanding of the following description and eliminate possible misunderstandings between frequency and phase measurements, that due to the small frequency deviations of the frequency FQ1 involved, the sampler CP performs a counter phase measurement C1 every 125 .mu.s, which is immediately converted to a frequency measurement, intended as a physical quantity and measured as a number of cycles within a time unit. A phase deviation caused by a change in frequency FQ1 or FQ2 is converted to a variation of the time instant where the counter C1 is sampled, then eventually to a different frequency value. The sampler CP provides anyway a frequency measurement, which, once processed, provides a phase measurement.
It is possible to go from a phase measurement to a frequency measurement through a simple integration, so that in fact the use of one or other quantity is generally a question of convenience and adequacy.
In the ET system, the coded signal U containing as such only the information supplied every 125 .mu.s, if the counting is 1687 or 1688, will be sent to the receiver R, which according to ETSI Standard converts the coded signal U in phase increments and decrements, so that 1687 will mean -1 cycle and 1688+1 cycle.
Since the receiver R uses the information from the coded signal U to operate on the phase locked loop PLL designed to work on the frame frequency, which is by far lower than 8 KHz, said phase locked loop PLL tends to follow the mean value of the sum of the phase increments and decrements determined by the coded signal U, thus obtaining the information of the frequency phase FQ1.
Therefore, according to ETSI Standard if the frequency FQ1 takes the rated value, a signal has to be supplied to the receiver R consisting of a coded signal U represented by a set of values such as eg. 0101010101, which, after an integration of any kind, such as for instance converting the set in phase increments and decrements, correspond to a constant phase value of -0.5 cycles, i.e. -.pi.. If, on the contrary, there is a phase shift of the frequency FQ1, this will be associated with the transmission of a sequence such as 01011010, which after integration in the receiver R performed by its digital loops will be-.pi., -.pi., .pi., .pi., corresponding to a whole cycle shift.
This means that using ET transmission system according to ETSI Standard, the receiver R may detect the frequency FQ1 with a one-cycle precision, whereas when the frequency deviation FQ1 is below this value no frequency deviation will be detected.
For clarity of illustration an example is here given starting first with the frequency rated values, where:
`0` stands for: 3374 cycles in 125 .mu.s PA0 `1` stands for: 3376 cycles in 125 .mu.s
true input frequency values to the counter C1: 1687.5 1687.5 1687.5. . . values counted by the counter C1:
1687 1688 1687 1688 1687 1688 1687. . . frequency measured by sampler CP (Modulo-2) and transmitted at a frequency of 8 KHhz:
0 1 0 1 0 1 0 cumulative phase measured, i.e. measuring and summing up phase increments: 0 1 1 2 2 3 3 actual phase: 0.5 1 1.5 2 2.5 3 3.5 phase difference between the measured phase and the actual phase: -.5 0 -.5 0 -.5 0 -.5 Now, as it can be seen, if this data is processed by multiplying by 2 and adding a suitable constant, eg. 0,5, a phase difference on the at 27 MHz flow is obtained: -0,5 0.5 -0.5 0.5 -0.5 0.5 -0.5 After all, it appears that the message being transmitted, i.e. a modulo-2 frequency measurement, represents a frequency coding with local errors but such to give the true value after being averaged. If the frequency of the data flow changes as compared with the frequency of the transmission flow (eg. slow increase), at a certain time the system will show a one-cycle phase difference. Counted values: 1687 1688 1687 1688 1687 1688 1687 . . . measured frequency (modulo-2) transmitted at the frequency of 8 KHz: 0 0 0 1 1 0 1 measured phase: 0 1 1 2 3 3 4 theoretical phase: 0,5 1 1.5 2 2.5 3 3.5 phase difference: -.5 0 -.5 0 -.5 0 -.5 phase difference (27 MHz) neglecting one constant (phase difference * 2 + 0.5): -0.5 0.5 -0.5 0.5 1.5 0.5 1.5
The mean value of this phase difference goes from a mean value `0` to a mean value `1`, achieving one-cycle resolution of the 27 MHz frequency.
High frequency phase shifts, the frequency being high as 4 KHz, are not detected by the loop PLL in the receiver, which is a lowpass filter with a lower equivalent band, i.e. surely lower than 1 KHz, working on the frame frequency.
A frequency drift of the same extent, measured over a 16 KHz frequency cycle, where the theoretical cycles counting is 843.75, has a half-cycle resolution.
A similar data source frequency measuring system is defined in the Recommendation ITU-T 1.363 concerning MPEG Standard (AAL1) (ATM Adaptation Layer type 1) as shown in FIG. 2.
An AAL system is there described, where the transmission flow FT is led through a frequency divider K, obtaining an output signal at a reduced frequency FTX, which feeds a modulo-16 counter C4. Thus, said modulo-16 counter C4 performs with 4 bits and outputs a 4-bit signal S4, whereas data flow FS goes through an adequate frequency divider DN, whose output has a sampling signal SC2 with a suitable frequency to drive the sampler circuit CP, which samples the 4-bit signal S4 and outputs the modulo-16 phase measurement SRTS. Said phase measurement SRTS is called Synchronous Residual Time Stamp and contains phase information for the receiver R.
The systems described above allow recovery of the data-source clock signal to the receiver apparatus, providing the phase measurement and using a phase locked loop PLL as already reported with reference to FIG. 1.
As to special frequency ratios, eg. as described in the publication IEEE Trans. Commun., Vol. 44, no. 6, pp. 742-748, June 1996 K. Murakami `Jitter in Synchronous Residual Time Stamp`, a low frequency `jitter` may be determined, i.e. a distortion due to synchronization errors, which is difficult to filter from the phase locked loop due to its low frequency. In other words, eg. with reference to ETSI Standard, cycle precision warranted by the Standard specifications implies that when the frequency information approaching the receiver deviates very slowly, namely a low frequency `jitter`, the receiver is unable to detect any frequency deviation in due time to avoid a distortion.
This may lead to an unacceptable synchronization of the signal received, specifically in the instance of a television signal particularly sensitive to temporary `jitter`.